Digital System [MCA-1] & [BCA]
Q1.Example of NOT gate:-
(a)
Solar
lamp (b) electrical supply
(c) laser light (d) none
Q2. What is the base of decimal, octal,
hexadecimal,binary numbers:-
(a)10,8,2,16 (b)8,10,16,2 (c)10,8,16,2 (d)2,8,10,16
Q3.1+1=___, 1+0=___
,0+0=____ ,0+1=_____What is the
results?
(a)0,1,0,1 (b)10,01,00,01 (c)11,1,0,1
(d)1,1,0,1
Q4.0*0=__,
0*1=___,1*0=___,1*1=____What is the results?
(a)0,1,1,1 (b)0,0,0,1 (c)0,1,1,0 (d)1,0,0,1
Q5.0-0=____,0-1=____,1-0=___,1-1=____What
is the results?
(a)00,01,01,00 (b)0,1,1,0 (c)both (a)&(b) (d) none
Q6.The _____ ,which has the highest weight, is called
the ________, and the _________, which has the lowest
weight,is called the ________.
(a)right most digit, most significant digit,left most digit, least
significant digit
(b)right
most digit, least significant
digit, left most digit,
most significant digit
(c)left
most digit, least
significant digit, right most digit ,
most significant digit
(d)left
most digit , most significant digit, right most digit, least significant
digit
Q7.The digits to the right side of the decimal point are known as______ and digits to the left side the decimal point are known as _____
Q7.The digits to the right side of the decimal point are known as______ and digits to the left side the decimal point are known as _____
(a)integer part ,fractional part (b)fractional part ,integer part (c)floating part, integer
part(d)both(b)&(c)
Q8.The position of bit
in a given sequence has a
numerical weight.it makes use of a _______
(a)binary point (b) decimal
point (c) octal point (d) all of these
Q9.IN repeated
division method , the first remainder is noted
down as ______ and last remainder
as ______
(a)MSB,LSB (b)LSB,MSB (c)integer ,fractional (d)floating , integer
Q10.This justifies
the usage of _______ in microprocessors, soft- computations, assemblers,
and in digital electronic application
(a)octal number system (b) binary number
system (c)hexadecimal number system (d) decimal number system
Q11. BCD code is also
known as :-
(a)8421 code (b)4 bit code (c)weighted code (d)none
Q12.Logic
AND,Logic OR,Logic NOT, Logic NAND,
Logic NOR, Logic Ex-OR, Logic Ex-NOR ,
follows the expressions:
(a)a.b ,a+b ,ā , (a+b)`,(a.b)`, āb+aЂ ,(a.b)`+(a.b)
(b)a.b , a+b ,(a+b)’ ,(a.b)’ ,ā
,ā.b+a.Ђ ,(a.b)’+(a.b)
(c)a+b ,a.b ,(a+b)’,(a.b)’,ā
,(a.b)’+(a.b) ,ā.b+a.Ђ
(d)a.b, a+b, ā, (a.b)’ , (a+b)’
, a.Ђ+ ā.b, (a.b)’+(a.b)
Q13(1).______ laws
are defined for OR and AND perations carried over the variablesmakes no
differences to OR and AND operations.
(2)_________ laws
states that’s that ,ANDing with one variable of the ORed
function , is similar to the ORing of ANDed results.
(a)associative law, commutative
law (b)commutative law , associative
law
(c) distributive law ,commutative
law (d)commutative law, distributive
law
Q14.a+1=___,
a.1=___,a.a=__,a+a=___,a.a’=____What is the
results ?
(a)1,a,a,a,0 (b)a,a,a,a,1 (c)1,1,1,1,1 (d)0,1,1,a,0
Q15.the complement of
a product form of an
expression is equal to the sum of the complements:-
(a)distributive (b) associative (c)
commutatative (d) none
Q16.____these gates
are universals gate.
(a)
NAND,NOR (B)OR ,NOR (C) AND ,NAND (D).EX-OR,EX-NOR
Q17.A-----------------Gate
also acts as a negative-OR gate.A----------Gate
also acts as a negative AND Gate.
(a)
NOR,NAND (B) AND,OR (c)NAND,NOR (d) OR,AND
Q18.
------------Theorems are used to represent the function only with universal
gates.
(a)
Demorgan’s (b) Distributive (c) Thenvien (d) None of the above
Q19.truth table simplification can be
done using ____
(a)sum of product (b)product of sum
(c) both (a)&(b) (d) minimize the expression
Q20.which is the falase statements:-
(a) it
simplification of the logic expression.(b)It produces the only SOP expression
(c)It it consists of 2n cells (d)
It only used for four variables
Q21.
__________ method is known as
tabular method.
(a) k-map (b)quine mclusky (c)truth table (d)none
Q22.how many half
adder used in full adder?
(a) 3 (b)2 (c) 1
(d) 5
Q23.A___ circuit is employed for
every column of bit addition
(a) half
adder (b) full adder (c) BCD adder (d) binary adder
Q24.____ gate is a basic comparator .
(a)AND (B) OR (c) EX-OR (d) EX-NOR
Q25.The basic function of a ________
is to detect the presence of a specified
combination of bits on its inputs and to indicate that presence by a specified out level.
(a)encoder (b) decoder
(c) multiplexer (d)
demultiplexer
Q26._______ code is unweighted code.
(a) BCD (b)binary (c) decimal
(d) none
Q27.The term _________ represents the
output changes the state any time with respect to the conditions on the input
terminals
(a). S-R latches (b) synchronous (c)asynchronous (d) cascaded
Q28.______ counter kniown as the
ripple counter.
(a) synchronous (b)asynchronous (c) ring counter (d)Jhonson counter (d) none
Q29.A
4-bit binary counter - ___
(a)IC 7493 (b)IC 7490
(c)IC 7495 (d)IC 74 94
Q30.decade consists of _____ and ____ asynchronous counter.
(a) 2 filp- flop , mod 3 (b)single filp-flop , mod 5, (c) double
filp-flop, mod 6 (d)none
Q31._____________ counter also known
as the Johnson counter.
(a) ring
counter (b)back counter (c) switch- back
counter (d) none
Q32.The jhonsons counter has _ states
in its sequence
(a) 2n (b)2n (c) n2
(d)none
Q33.In BCD addition answer is greater
than ____ then invalid
(a) 6 (b)9 (c)15 (d)none
Q34.
______ of ADC is also called as thecounter type and_________
ADC is also known as parallel counter.
(a)flash counter ,slop type (b)
successive approximation, slop type
(c)flash type, staircasetype (d)
digital ramp , flash type
Q35.a three stage jhonson counter, driven by a _______hertz
clock would generate three __ phased
square waves at _____hertz
(a)120,60,360 (b)360,120, 60 (c)60,360,120, (d)360, 60,120
Q36.______ is which output of the last
stage is fed back
(a)ring counter (b) Johnson
counter (c) universal counter (d)none
Q37.________shift register may be one
to 64 bits in length, longer if registers or packages are cascaded
(a)serial in ,parallel out (b) serial in, serial out
(c)parallel in, parallel out (d) parallel in serialout
Q38.UP/DOWN counter is also k/as ___
(a) below &above counter (b)
above &below counter (c) bidirectional
(d) none
Q39.______ filp -folp is used for synchronous counter.
(a) J-K filp flop (b) D flip flop (c) S-R filp-flop (d) none
Q40. mod –N where N represents ___
(a) number
of filp- flop (b) number of stages (c) number of counting (d) none
(b)
question
41-60 have 2 marks.
Q41. The ____state
of counter sequence in the variable modulus counter is known as terminal count.
(a) starting state
(b)middle state (c) half of mid
state (d) final state
Q42.A single flip flop used
gives ___ states output and refferd to as ____
(a) 1,
mod 1 (b) 2, mod 2 (c) 1,mod 2 (d) 2,mod 1
Q43.
_______ is one in which the flip-flop are not simultaneously triggered.
(a) ripple counter
(b)synchronous counter (c)ring counter (d) none
Q44.The total modulus of a cascading
arrangements is the _____of the
individual modulus of all cascaded counters.
(a) sum (b)difference (c) division
(d ) product
Q45.In UP/ down counter If up/dowm=1 then clock signal to___ is __
(a) first
filp- flop, Q1 (b) first filp-flop, Q’1 (c)second filp-
flop,Q1(d)second filp_flop,Q1’
Q46. In asynchronous counter
______gate whose output is connected to the clear pin.
(a)OR (b)AND
(c)NAND (d)none
Q47.______ is known as the pluse triggered filp-flop.
(a) S-R
filp-flop (b)J-K flip- flop (c)master_ slave flip-flop (d)D flip- flop
Q48.when J=0,k=1 then output is:-
(a) set (b) reset
(c) toggle (d) no changes
Q49.Edge triggered is also known as ____
(a) static triggering
(b)dynamic triggering (c) clock
triggering (d) state triggering
Q50.An NOR gate
_____ can be constructed .
(a)active low (b)active high (c)neither (a)nor (b) (d) active middium
Q51. In T filp- flop if T=0
then Output is __
(a)complements of previous
state (b) invalid state (c) previous state (d)toggle state
Q52.Latches are bistable elements
whose state normally depends on __ inputs.
(a) synchronous
(b)asynchronous (c) neither (a)nor (b) (d)binary values
Q53.One filp- Flop output can be:-
(a) 00,10 (b)10,01 (c)0,1 (d) all
Q54.A counter which goes through all the possible states before
restarting is called as___
(a)asynchronous counter (b)synchronous counter (c) ring counter(d)full moduluscounter
Q56.o design an asynchronous counter
to count till.M find the number of filp- flops required.
(a)n=log2 M (b) n=2M (c)M=2n (d)none
Q57.A mod-6 counter uses ____
filp-flop.
(a) 2 (b)6 (c)5
(d)none
Q58.The basic principle of cascading
the counter is to have known ___ of the
input clock signal.
(a)
multiplexing division (b) frequency division (c) counting
division (d)parallel division
Q59.4-stage ring counter divides
by ___
(a) 4
(b) 8 (c) 2 (d) 16
Q60. four data bits will be shifted
“data in” by four clock pulses and be available
at QA through QD _____
(a) lamps (b) horns (c)LED
(d)all
61-75 question having 4 marks:
Q61.negative edge triggered ripple up/down for 2 bit.used then inputs of the seconds filp- flop.
(a) Q1*(up/down) (b)Q1*(up/down)+Q1’*(up’/down’)
(c) Q1*(up/down)+Q1’*(up/down)’(d)
none
Q62.
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Clock pulse
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For UP counting up/down
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For down counnting
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Qc
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Qb
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Qa
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Qc Qb Qa
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0
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0
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0
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0
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1
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1
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1
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||||||||
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1
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0
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0
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1
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1
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1
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0
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2
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0
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1
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0
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1
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0
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1
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3
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0
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1
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1
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1
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0
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0
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4
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1
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0
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0
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0
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1
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1
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5
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1
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0
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1
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0
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1
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0
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6
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1
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1
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0
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0
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0
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1
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7
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1
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1
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1
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0
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0
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0
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These
counter filp-flop have a
inputs:-
(a)For FFA J=k=1,for FFB j=k=QA.UP+ QA’
down for FFC J=k=QAQBQc.
(b) for FFA J=K=QA.UP + QA’.down ,for FFB J=K=1 ,for FFC J=K =QA.QBQc
(c)for FFA J=K=1, for FFB QA .UP+
QA’. down, for FFC J=K =QA.QB.UP+ QA’.QB’.down
(d) for FFA J=K=1, for FFB QA .down+
QA’. UP, for FFC J=K =QA.QB.UP+ QA’.QB’.down
Q62.in active low S-R latches when S=0, R=0, then___________
When S=0 ,R=1 then____ , When S=1, R=0
then ______, when S=1,R=1 ,then_____
(a) invalid
,reset, set ,no change (b)no change, reset, set,invalid
(b) invalid,
set, reset, no change (d) no change, set, reset, invalid
Q63.true and flase:-
(1). The stages in a shift registr are delay stages , typically type “T”
flip-flop and “S-R” flip-flop(T/F)
(2) in shift-register we used asynchronous clock(T/F)
(3) multiplexer is also known as the
multiple output device(T/F)
(4)shifting is possible 4 type:up
shifting, down shifting, left shifting, right shifting
Q64.IN universal shit register
(LD/SH)’controls the ______ at the data input to the FF’sand 74LS395 perform
the______
(a) AND-OR
demultiplexer , left shifting (b)AND
decoding , right shifting
(c) AND-OR multiplexer,
right shifting (d) AND encoding, left
shifting
Q65.when pin EN is HIGH the input Sand
R control the output of the flip- flop ,then gated latches of these types are also known as ______________
(a) edge
triggered (b)level triggered
(c)neither(a)nor (b) (d)statetriggered
Q66.In
synchronous decade counter UP
counter FFB changes on each time when
________
(a) QA=1,QD=0,QB=1,Qc=1 (b) QA=1,QD=0,QB=1
(c)QA=1QD=0,Qc=1 (d)QA=1, QD=0
Q67.In three –bit Synchronous Binary UP- counter-
Q67.In three –bit Synchronous Binary UP- counter-
Qc changes state only when Q A
=___,Q B =___. This is been realized with an ____ gate logic.
(a) 1,0,
NAND (b)0,0 NAND (c)1,1, AND (d)0,0,AND
Q68.IN
three bit synchronous down counter
Qc changes state only wnen
Q A =___,Q B =___.
This is been realized with an ____ gate
logic.
(a) 1,0, NAND (b)0,0 NAND (c)1,1, AND (d)0,0,AND
Q69.Loading binary 1000 the perform
the ______ .if we want to same
output after 8 time shifting.
(a)serial in serial out (b)ring shifting (c) jhonson shifting (d) parallel in parallel out
Q70.which of them true statement:
(a) flip
flop is combinational circuit
(b) AND
gate is used as basic decoding element
(c) Shift
register only perform by multiplexer.
(d) Nyquist frequency , equal to one –four of ADC
‘s sample
Q71.give the NAND realization of
Boolean expression
f=a.b+a.c+b.c
_________
_________
_________ ___ __
___ __ __
__ __ __
__
(a)a.b+a.c+b.c (b)a.b+a.c+b.c (c)a.b. a.c . b.c (d)a.b .a.c .bc
Q72.∏M(0,4,9,10,11,14,15) reduce the K-MAP
(a)a+c’+d’. b+c’+d. a’+d. a’+c
(b)a.c’d’+b.c’.d+a’.d+a’.c
(c)a.c+a’.c’.d’+ab’ (d)a+c.a’+c’.a+b’
Q73. To implement the operations
specified in the following in the truth table.
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Inputs
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output
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||
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A
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B
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C
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f
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0
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0
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0
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1
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0
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0
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1
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0
|
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0
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1
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0
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0
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0
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1
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1
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1
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1
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0
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0
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1
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1
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0
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1
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1
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1
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1
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0
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1
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1
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1
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1
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0
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(a) a’b’c’+a’bc+ab’c’+ab’c+abc’ (b)a’b’c+a’bc’+abc
(c)a’b’c’+abc+a’b’c
(d)a’b’c’+a’b’c+a’bc’+ab’c+abc
Q74.
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Inputs
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output
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||
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A
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B
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C
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f
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0
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0
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0
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0
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0
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0
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1
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0
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0
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1
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0
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0
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0
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1
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1
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1
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1
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0
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0
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0
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1
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0
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1
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1
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1
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1
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0
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1
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1
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1
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1
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1
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Simply using Karnough Map.
(a)a’bc+ab’c+abc’+abc (b)ac+ab+bc
(c)abc+acb’ (d)b’c’+a’b’+a’bc’
Q75.1001+1001 using parallel adder then get output:
(a)S0=0 c0 =0 , S1=1 c1 =0, S2=0 c2 =1, S3=1 c3 =0
(b) S0=0 c0 =1 , S1=1 c1 =0, S2=0 c2 =0, S3=0 c3 =1
(c) S0=1 c0 =0 , S1=0 c1 =1, S2=0 c2 =0, S3=1 c3 =0
(d) S0=0 c0 =1 , S1=0 c1 =0, S2=1 c2 =0, S3=1 c3 =0
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